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Intern - Esd Engineer

Micron Technology

Intern - Esd Engineer

Boise, ID
Internship
Paid
  • Responsibilities

    Intern - ESD Engineer * Apply now * Start apply with LinkedIn * Start apply with Facebook * Apply Now Email * Please wait... Date: Mar 19, 2018 Location: Boise, ID, US Company: Micron Req Id: 114761 Project: Learn how to apply the ANSYS software tool PathFinder to identify potential ESD design problems for any new Micron memory design. ESD or Electrostatic Discharge is defined as a transfer of charge between two bodies at different electrostatic potentials, either through direct contact or via ionized ambient discharge (a spark). The intern will be responsible to view and export full memory chip designs from Cadence layout tool into the ESD Pathfinder tool. After the selected layout cells have been imported into Pathfinder, the intern will be responsible for creating all necessary files in Pathfinder so that an ESD engineer can use this ESD tool to find any highly resistive nets or find where the current density in the metal interconnects are at maximum values. The summer college intern will need to learn the following: 1. Basic 101 Fundamentals of ESD design 2. Semiconductor physics of ESD circuits and metal interconnects 3. Different types of short transient high current & voltage ESD discharge events 4. Semiconductor manufacturing flow from wafer starting materials to finished electronic package devices 5. Understand ESD testing and understand what type of circuits are damaged and why they are broken 6. Cadence layout CAD tool 7. Ability to generate .gds files from cadence so they can be imported into the ESD Pathfinder tool 8. Understand how ESD design rules are generated and how PathFinder applies these rules to check the layout of a memory design. 9. Ability to work with the ESD engineer using Pathfinder to find potential ESD problems with the metal interconnects for a new design Education 1. Masters or PhD Electrical Engineering 2. Focus on semiconductors 3. Preferred candidates are working for Dr. Juin J. Liou at UCF or Albert Wang UCR 4. Candidate should have used layout tools in both undergrad and graduate studies 5. Strong Electrical Engineering background 6. Strong background in semiconductor design and semiconductor process We recruit, hire, train, promote, discipline and provide other conditions of employment without regard to a person's race, color, religion, sex, age, national origin, disability, sexual orientation, gender identity and expression, pregnancy, veterans status, or other classifications protected under law. This includes providing reasonable accommodation for team members' disabilities or religious beliefs and practices. Each manager, supervisor and team member is responsible for carrying out this policy. The EEO Administrator in Human Resources is responsible for administration of this policy. The administrator will monitor compliance and is available to answer any questions on EEO matters. To request assistance with the application process, please contact Microns Human Resources Department at 1-800-336-8918 (or 208-368-4748). Keywords: Boise || Idaho (US-ID) || United States (US) || Technology Development || Entry || Internship || Engineering || #LI-MT1 || Nearest Major Market: Boise Nearest Secondary Market: Meridian Job Segment: Semiconductor, Intern, Manufacturing Engineer, Engineer, Electrical, Science, Entry Level, Engineering * Apply now * Start apply with LinkedIn * Start apply with Facebook * Apply Now Email * Please wait...

  • Industry
    Manufacturing