Physical Design Engineer - Chip Level Floorplanning Job Detail Job Id E1966893 Job Title Physical Design Engineer - Chip Level Floorplanning Post Date 09/27/2018 Company - Division Qualcomm Technologies, Inc. - CDMA Technology Job Area Engineering - Hardware Location California - San Diego Job Overview As a chip level floorplan team member, ability to work in different aspects of chip level floorplaning and integration which includes top level partitioning, pins assignment, feedthrough, power grid generation, cpf/upf based flows. Interact with packaging team for bumps assignment and work on the chip level RDL work and IR Drop closure loop. Support physical verification activities. Interact with CAD team to develop/enhance flows. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company. Minimum Qualifications * Bachelor's degree in Science, Engineering, or related field. * 2+ years ASIC design, verification, or related work experience. Preferred Qualifications 2+ years of experience in: * Entire PD flow from netlist to GDS (Floorplanning, power planning, placement & pptimization, CTS, routing, post route optimization and DRC closure) * Experience in chip level partition flow, pins assignment, time budgeting and feedthroughs * Experience using different techniques for low power designs and UPF/CPF flows * Experience of 14nm/10nm designs to understand complex design rules in latest technology nodes and physical verification * Automation skills using Perl and tcl and able to develop/support flows related to floorplanning , integration and design validation * Masters degree in Electrical or Computer Engineering * Experience with Cadence tools (First Encounter, Innovus) Education Requirements Required: Bachelor's, Computer Engineering and/or Electrical Engineering Preferred: Master's, Computer Engineering and/or Electrical Engineering Keywords You will need to login into your profile to apply for this job. If you are a new user, click here to create a profile. Messages