Summer 2026 Internship: Explorations of AI Application for Automated Layout Generation and Correction
An internship at onsemi offers a dynamic opportunity to gain hands-on experience through real-world projects that drive innovation in the semiconductor industry. Interns are entrusted with meaningful responsibilities and exposed to cutting-edge technologies, fostering both technical skill development and professional growth.
onsemi views internships as a strategic pipeline for entry-level career positions, providing a collaborative and inclusive environment where interns work alongside diverse teams and contribute to high-impact initiatives. The company's commitment to sustainability, including its goal of achieving net-zero emissions by 2040, enables interns to engage in projects that align with global environmental priorities.
Key benefits include:
Internship roles span multiple disciplines including engineering, business operations, data analytics, and finance, and are designed to align with onsemi's strategic goals of innovation and workforce development. Structured programs such as rotational field sales and finance analyst tracks offer additional career pathways for interns transitioning into full-time roles.
Currently enrolled in Master of Science in Electrical Engineering (MSEE) or relevant technical degree; enrollment in a PhD program is preferred.
Solid understanding of semiconductor device physics, including MOSFET, BJT, resistor, capacitor, and diode operation.
Familiarity with semiconductor layout development in the Cadence Virtuoso environment.
Previous research experience using AI tools and agents; experience of developing AI tools is a plus.
Programming experience in scripting languages is a plus.
Strong troubleshooting, root-cause analysis, and problem-solving skills.
Ability to communicate complex technical concepts clearly to cross-functional teams.
Here at onsemi we take great pride in our internship program and the efforts we take to provide students with hands-on industry experience. We provide competitive pay medical benefits, various networking event opportunities, and flexible hours based on school schedule.
Currently enrolled in Master of Science in Electrical Engineering (MSEE) or relevant technical degree; enrollment in a PhD program is preferred.
Solid understanding of semiconductor device physics, including MOSFET, BJT, resistor, capacitor, and diode operation.
Familiarity with semiconductor layout development in the Cadence Virtuoso environment.
Previous research experience using AI tools and agents; experience of developing AI tools is a plus.
Programming experience in scripting languages is a plus.
Strong troubleshooting, root-cause analysis, and problem-solving skills.
Ability to communicate complex technical concepts clearly to cross-functional teams.
Here at onsemi we take great pride in our internship program and the efforts we take to provide students with hands-on industry experience. We provide competitive pay medical benefits, various networking event opportunities, and flexible hours based on school schedule.
onsemi is seeking a skilled intern in our Gresham, OR, site with a strong interest in explorations of practical AI applications in semiconductor technology development. The ideal candidate needs to have a solid foundation in semiconductor device physics and a software programming background. The intern will develop and optimize automated layout generation flow using existing AI tools.
This internship role spans multiple disciplines including engineering and data analytics and is designed to align with onsemi's strategic goals of innovation and workforce development. This is a full-time in person internship.
Generate P-Cell layouts for next generation devices using Cadence SKILL code
Develop automation flows for P-Cell layout generation using AI engines
Build AI agents and platforms for new P-Cell layouts with specific design
Midterm/final report and presentation
onsemi is seeking a skilled intern in our Gresham, OR, site with a strong interest in explorations of practical AI applications in semiconductor technology development. The ideal candidate needs to have a solid foundation in semiconductor device physics and a software programming background. The intern will develop and optimize automated layout generation flow using existing AI tools.
This internship role spans multiple disciplines including engineering and data analytics and is designed to align with onsemi's strategic goals of innovation and workforce development. This is a full-time in person internship.
Generate P-Cell layouts for next generation devices using Cadence SKILL code
Develop automation flows for P-Cell layout generation using AI engines
Build AI agents and platforms for new P-Cell layouts with specific design
Midterm/final report and presentation