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Verification Engineer

Allstaff Solutions

Verification Engineer

San Jose, CA
Full Time
Paid
  • Responsibilities

    Summary

    AllStaff Solutions is an established IT and Healthcare Services firm and we love what we do! Our team strives for success and it makes our day when we are able help talented individuals find their career’s next move and our clients find qualified talent. If you are interested in joining the AllStaff Team, please apply or submit your resume for review today!

    Job Title

    Verification Engineer

    Location

    San Jose, CA

    Duties & Responsibilities

    IBM’s brain-inspired computing group, with a U.S Government Customer, has a need for an experienced verification engineer. This engineer will assist in the development, implementation and testing of a digital neuromorphic accelerator chip. The selected candidate will work directly with other designers and system architects to verify and debug pre-silicon logic under the supervision of IBM’s team lead.

    • Collaborate with logic and verification team members in a dynamic environment

    • Create detailed test plans to verify complex digital blocks from functional specifications

    • Work closely with design engineers to identify coverage holes and deliver functionally correct blocks

    • Create coverage measures and identify corner cases

    • Create UVM-based test benches from scratch

    • Generate UVM-based test environments for logic designers

    • Create functional coverage in SystemVerilog

    • Setup, maintain, and operate batch regression environment

    • Simulate and debug SystemVerilog designs

    • Run formal verification tools

    • Document and support test plans reviews

    • Setup and maintain verification tools in linux

    Requirements

    • Experience with SystemVerilog with assertions, UVM test benches

    • Experience with C and C++ and scripting languages

    • Experience with linux environment

    • Familiarity with industry standard ASIC EDA tools, including logic simulators, and debuggers

    • Familiarity with formal verification and linters

    Other Details

    • At least 3 year experience in any of the following: SystemVerilog, UVM, SystemC, Verilog or VHDL

    • At least 1 year in C++/Python and Object Oriented Methodology

    • Experience with DFT

    • Experience with the simulation and verification of a system including 3rd party IP

    What we Offer

    Competitive pay and benefits

    How to Apply

    Please submit your resume below for this opportunity and to view other positions available, visit our career’s page at http://jobs.crelate.com/portal/allstafftechnicalsolutions

    AllStaff Solutions is an equal employment opportunities (EEO) employer and terms of employment are without regard to race, color, religion, sex, national origin, age, disability or genetics. AllStaff Solutions complies with applicable state and local laws governing nondiscrimination in employment. This policy applies to all terms and conditions of employment.