ASIC Design Engineer Intern Location Santa Clara, US REQ # 591 Job Number I1901 Position Responsibilities: Developing micro-architecture specifications for a next generation media processor. Designing and implementing video compression logic, image processing logic and processor cores in Verilog and SystemVerilog. Synthesize and optimize RTL for timing, area and power. Developing unit level and cluster level test-benches, BFMs, random test generators, functional coverage monitors, using system verilog, UVM, C++, and perl scripts. Developing test plan, random and directed test cases, performing logic verification, and functional coverage analysis. Developing frontend methodologies and tool flows. Participating in chip bring up. Requirements: Masters degree in Electrical Engineering with 0-5 years of experience. Good understanding of computer architecture, logic design and VLSI design. Knowledge of SystemVerilog, Verilog and Perl. Knowledge of design verification, and functional coverage. Ability to program scripting languages and the ability to write assembly language programs. Strong communication skills and a good team player.