Job Description

We are looking for a motivated individual to join our FPGA Design Team at our headquarters in Santa Clara, CA, in the heart of Silicon Valley. In this position, you will be responsible for designing test bench, simulating, and testing FPGA RTL code that forms the backbone of our next generation systems.

Job Responsibilities:

• Create and maintain test benches in Verilog/SystemVerilog
• Create BFM, RTL models for new and existing designs
• Develop the verification test plans and test cases
• Review the design functional coverage

Concepts and Skills:

• Data and control architectures of a modern ethernet switch, including chip IO interfaces such as Interlaken, Ethernet PHY/MAC, PCIe, SMBus, SPI, MDIO, JTAG, etc.
• Protocols using Ethernet, such as PTP, SFlow, POE, etc.
• Simulation software for FPGA functional verification

Qualifications

• 2-4 years of designing Verilog/SystemVerilog RTL code
• Proficient in design verification tools and languages (SystemVerilog, SVA, Modelsim, Perl, Python, Unix shell scripts)
• Experience in the chip level verification environment setups, code/functional coverage collection
• Motivated, passionate, with sense of urgency and commitment to achieve the targeted goals
• Strong scripting, debugging and problem solving skills
• Excellent in-person, video, and written communication skills

Additional Information

The new hire base pay for this role has a salary range of $130,000 to $180,000. The actual salary offered will be based on a wide range of factors, including skills, qualifications, relevant experience, and US location. The salary range provided reflects the base salary and in addition may also be eligible for discretionary Arista bonuses, commissions, equity, and benefits including medical, dental, vision, well-being, tax savings, and income protection.

All your information will be kept confidential according to EEO guidelines.