Job Description
Our Client is a fabless SOC design company delivering advanced storage solutions with direct applications into the Artificial Intelligence and Big Data markets. They are recognized as an emerging leader in system performance, reliability, efficiency, and security. Headquartered in the Silicon Valley with office in the US and Asia they have been stealthily growing over the past 5 years and now are greater then 200 employees worldwide.
In this role you will leverage your technical expertise in Verification, Verilog, SystemVerilog and UVM to:
LOCATION:
San Jose, CA
*Relocation assistance will be provided
THINGS TO CONSIDER:
Title: Verification Design Engineer – (Sr Principal, Principal, Staff, Sr, Lead title will be determined based on candidate)
Offers a very competitive comp package including Base, Bonus, Private Equity, 401K, Health and other benefits
Well established start-up business with more than 5 years of success and 200+ employees backed by both Venture Capital and strong existing Product revenue
Global company with offices in North America, and Asia
Cutting edge storage solutions which provide challenging and unique development opportunities.
Great Career growth opportunity with opportunity to function as Lead if desired
New position in the company as a result of strong growth and new business..
Company is expecting to IPO within the next 1.5 years; generous equity package is offered to new hires