Job Description

Job Posting: (  ITEKJP00023491, Intel Corporation)

Job Title: Failure Analysis  Technician

Location: San Jose CA USA 

Shift:  1pm - 10pm 

Contract: 05 months 

 DESCRIPTION:

Semiconductor package/silicon sample prep. for failure analysis using CNC, polishing and other lab equipment. Person will be responsible for logistic between two Intel building in San Jose/Santa Clara (~5 miles distance one way - driving own vehicle once or twice per day only). Help engineers with routine analytical equipment setup, test and calibration as well as routine maintenance. In this position, you will support hands-on work to electrical FAFI and physical silicon debug Lab operation. Performing hands-on sample prep. using polisher, CNC and various equipment for FAFI and silicon debug of Intel's NG products manufactured on advanced packaging and fab process technology. Performing hands-on test data collection using tester (CMT/HDMT), Parametric Analyzer, Oscilloscope and curve tracer. Logistical support of transporting packaged IC parts between Intel Labs within short distance. Collecting board level and package level IREM data under engineer's supervision after training. QUALIFICATIONS:

AA in science or diploma or equivalent Optional experience: Knowledge of CMOS-VLSI circuits, electronics, device physics and Fab process flows. IC Board/system level testing knowledge and problem solving. ATE/CMT Tester usage experience is a plus. Knowledge in LINUX, Microsoft Office (Outlook, Excel, Word, Power Point, Project) is required. Excellent verbal and written communication skills along with operating independently with minimum supervision.