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FPGA SV/UVM Verification Engineer

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DBSI Services

FPGA SV/UVM Verification Engineer

Cedar Rapids, IA
Full Time
Paid
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  • Responsibilities

    Role- FPGA SV/UVM Verification Engineer

    Location- (REMOTE) Need basis he needs to travel Cedar Rapids, Iowa

    Job Details:

    Roles and Responsibilities:

    · 5+ Years of FPGA Requirement based Verification

    · Experience with System Verilog

    · Experience with Test Bench Creation, Test Bench Troubleshooting, Test Case development, Test Procedure Development and result analysis

    · Experience with UVM

    · DO-254 Process knowledge is desired

    · Video/Image Processing Project Experience

    This is a remote position.