Benefits:

401(k)

401(k) matching

Relocation bonus

Title – Senior Design Verification Engineer Location: Remote

Job description

Key Responsibilities:

Verifying the FPGA RTL for complex digital blocks.

Writing the verification plan.

Developing verification environments to support FPGA IP level verification in constrained-random and/or directed verification environments using System Verilog & UVM according to the functional/code coverage goals.

Required Experience:

SystemVerilog and VHDL.

UVM expertise. Able to Create UVM agents and other UVM components such as prediction models (without any templates or frameworks).

Requirement based verification.

Preferred Experience:

DO-254.

Component-level verification: the candidate would be working on block levels.

Requirements management tool, such as Doors.

Ethernet and AXI-Lite/AXI protocols.

Xilinx/Microsemi FPGA knowledge.

This is a remote position.