Job Title: Low Power Design Verification Engineer

Location: Remote work

Duration: 7 months W2 contract, possible extention or conversion

Leading Social Media Company

Duties:

Responsible for low power verification including both dynamic and static verification

Write and augment existing testplans.

Implement testbench and scoreboards / checkers.

Implement test sequences as per plan and debug failures

Achieve 100% functional, code, and power coverage

Work closely with designers, micro architects & f/w to resolve issues

Ability to communicate & articulate clearly progress / issues with project leads

Skills: Must Have:

7+ years of proven experience as a DV engineer

Implied: Candidate will have hands on Experience with executable test plans and Coverage Driven verification

Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology)

Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools

Experience with UPF based simulation flow

2+ Years of experience with C/C++

Wish List/ Nice to Have:

Experience with Power Aware GLS flow

Tcl and Python (or similar) scripting language

ASIC design experience

MSEE/CS or equivalent experience

Education:

Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science

Master's Degree preferred but not required

Required Skills:

BSEE

VERILOG

SIMULATIONS

SYSTEM VERIFICATION

OBJECT ORIENTED PROGRAMMING

Additional Skills:

APPLICATION-SPECIFIC INTEGRATED CIRCUIT

ASIC

ASIC DESIGN

CADENCE

ALGORITHMS

CODING

DEBUG

MSEE

PYTHON

SCRIPTING

SYNOPSYS

TCL