Job Description

THIS ROLE COVERS ALL ASPECTS OF FPGA DESIGN DEVELOPMENT PROCESS INCLUDING: DESIGN PLANNING/ARCHITECTURE, DEVELOPING PLATFORM/SYSTEM FUNCTIONALITIES IN FPGA RTL USING VERILOG / SYSTEMVERILOG, RTL SIMULATION, LOGIC OPTIMIZATION, SYNTHESIS, FPGA FLOORPLANNING, TIMING CLOSURE AND DOCUMENTATION. A SOUND UNDERSTANDING OF RTL AND FPGA DESIGN PRACTICES IS IMPORTANT.  

Qualifications

**10+ YEARS OF EXPERIENCE IN THE FOLLOWING: • HANDS-ON FPGA DEVELOPMENT EXPERIENCE INCLUDING SYNTHESIS, PLACEMENT, OPTIMIZATION AND TIMING CLOSURE. • HANDS-ON VERLIOG AND/OR SYSTEMVERILOG EXPERIENCE. • EXPERIENCE WITH SIMULATION TOOLS LIKE MODELSIM FOR DESIGN VERIFICATION. • EXPERIENCE WITH SCRIPTING LANGUAGES TCL, OR PERL, OR PYTHON. • EXPERIENCE WITH DESIGN VERIFICATION, DEBUG & ALSO VALIDATION AT PLATFORM/SYSTEM LEVEL

Additional Information

B.S. OR M.S. IN ELECTRICAL ENGINEERING, COMPUTER ENGINEERING OR AN EQUIVALENT FIELD.