Job Description

Reporting to the Manager of FPGA – Imaging, this engineer will play a role in delivering best-in-class image processing solutions for our da Vinci systems, as part of a strong cross-functional team. The engineer in this position will work with the broader Vision team to architect, implement and verify image processing algorithms to FPGAs deployed on the platform. This includes components in the entire processing pipeline: from image sensor data acquisition to stereo displays.

The ideal candidate will possess a strong background in hardware-based video/image processing with an understanding of image processing algorithm selection, implementation, and evaluation with the trade-offs between visual quality, performance, and FPGA resource utilization in mind.

RESPONSIBILITIES

• Play a role in definition and FPGA implementations of high-performance image-processing pipelines
• Collaborate with other experts in imaging to craft the best trade-offs in resources, cost, performance, and practicality to create optimal video processing architectures
• Work with other contributors in the FPGA space to harmonize the video processing implementation with established best practices
• Implement video processing designs using (System)Verilog and High Level Synthesis (HLS)
• Verify via simulation and on systems, the implemented designs
• Optimize performance of image processing designs on systems
• Collaborate on improvements to FPGA design and verification methodology

Qualifications

QUALIFICATIONS

• 5+ years of relevant experience and Bachelor's Degree; or 3+ years of experience and a Master's Degree; or a PhD with no experience; or equivalent work experience
• Experience in FPGA design implementation/verification and familiar with common image processing techniques
• Ability to map complex image processing algorithms to FPGA-efficient implementation
• Experience with Verilog and SystemVerilog constructs such as interfaces, structs, etc.
• Experience with C or C++
• Experience with Vitis HLS or Catapult HLS is highly desired
• Understanding of and experience with high-speed digital design and associated challenges
• Understanding of static timing analysis/timing constraints and experience with bus protocols (AXI4 Streaming, AXI4 Memory Mapped, AXI4-Lite)
• Familiarity with at least one scripting language such as Python or Tcl
• Familiarity with modern RTL verification methodologies (SystemVerilog, UVM/OVM) is a plus
• Experience with revision control software e.g. Git

We provide market-competitive compensation packages, inclusive of base pay, incentives, benefits and equity, and the anticipated pay rate for this position is $128,800 to $185,400. It would not be typical for someone to be hired at the top end of range for the role, as actual pay will be determined based on several factors, including location, skills, and experience level.

Additional Information

Due to the nature of our business and the role, please note that Intuitive and/or your customer(s) may require that you show current proof of vaccination against certain diseases including COVID-19.  Details can vary by role.

Intuitive is an Equal Employment Opportunity Employer. We provide equal employment opportunities to all qualified applicants and employees, and prohibit discrimination and harassment of any type, without regard to race, sex, pregnancy, sexual orientation, gender identity, national origin, color, age, religion, protected veteran or disability status, genetic information or any other status protected under federal, state, or local applicable laws.

We will consider for employment qualified applicants with arrest and conviction records in accordance with fair chance laws.