Job Description

The Principal RFIC Design engineer will be responsible for the development of RF Front-End Integrated Circuits, including PA, LNA, Switch, Filter, Phase Shifter, and other circuits in BULK CMOS and/or SOI CMOS and/or SiGe BiCMOS processes. These ICs will be used in mmWave 5G Infrastructure (Base stations, Picocells, Microcells, Femtocells), Repeaters, Consumer Premise Equipment (CPEs), and 5G Handheld wireless devices, including mobile phones. These devices will operate in sub 6GHz, and 24-44GHz Millimeter-wave frequencies.

Responsibilities include architecture, planning, design, simulation, verification, and production ramp support of highly integrated, high volume RFICs for high-growth, fast-paced, and competitive wireless handset, tablet, and IoT markets. In-depth knowledge of PA, LNA, Switch, Filter, and phase shifter circuit design and module design of wireless systems are a MUST. Familiarity with cellular standards will be useful. The candidate must be able to work well with other design engineers, system engineers and CAD layout designers. The candidate will face challenging tasks in order to meet critical performance parameters in the design state-of-the-art PAs, LNAs, Switches, phase shifters and Filters. Very good understanding of semiconductor physics and strong circuit simulation skills utilizing the Cadence and ADS environment are necessary. Candidate is expected to understand and lead complex designs.

JOB REQUIREMENTS: •MSEE and minimum 10 years of high frequency millimeter-Wave RF IC design experience required, Ph.D. preferred •Demonstrated RF IC design experience using BULK CMOS, SOI CMOS, SiGe BiCMOS •Understanding of associated analog control and bias circuits •Experienced in implementing on-chip ESD protection strategies for HBM/MM/CDM on RFIC and good understanding of system level IEC ESD requirements •Strong understanding of silicon fabrication and how it affects the device physics, device model, and circuit performance •Strong understanding and practical expertise of both on-die and in-package coupling mechanisms is required, including modeling and simulation using EM simulations at the die and package level •Demonstrated experience debugging, resolving and applying techniques to mitigate analog/RF/mixed signal noise issues and RF coupling, shielding, and grounding •Proficient with Cadence Spectre (RF), GoldenGate, BDA and ADS simulation tools (Sparameter, HB, envelope) •Experience with EM simulation tools such as HFSS or EMX •Strong understanding of packaging techniques such as wire bonding (single chip and multi-chip packages) and flip-chip technologies for RF products and their impacts on design •Experience with Smith chart, load and source pulling, RF matching, transmission lines in both simulation and lab environment •Layout experience using the Cadence flow, including LVS and DRC. Ability to work with CAD engineers and provide guidance on RF and analog layouts •Knowledgeable of all RF parameters such as stability, return loss, harmonics, IMD, P1dB, NF, switching speed, IIP2/3, and ability to design and optimize for each parameter •Strong hands on experience of lab equipment including RF signal generators, oscilloscopes, power amplifiers, filters, duplexers, diplexers, spectrum analyzer, power sensors, and VNAs is required

Company Description

Located in Irvine, California, Mobix Labs is a highly innovative, IP rich, and dynamic Fabless Semiconductor company focused on developing cutting-edge, fully integrated, Bulk CMOS, single-chip, single-die, mmWave Beamformers, antenna solutions, and RF Semiconductors for 5G and Beyond.