Responsibilities:

Develop Verilog and VHDL designs to validate the function of Synthesis tools, both internally and externally developed.

• Analyze the results of synthesis operations to debug failures with the tools.
• Read and analyze specifications for new synthesis features
• Develop comprehensive test plans for testing synthesis features as well as validating software core flow following synthesis steps
• Take ownership of existing synthesis test plans as a base upon which to build new tests
• Maintain documentation of test results to assist in debugging and modification of software
• Test for integration and overall quality on OEM synthesis products
• Consult with development engineers in resolution of problems

Qualifications:

• BS/MS/PhD Electrical Engineering or Computer Science.
• 5+ years experience with HDL Synthesis tools.
• Design experience using VHDL and Verilog required.
• Knowledge of standard defect tracking and test automation preferred.
• Knowledge of automatic test vector, design generation using VHDL or Verilog and scripting for  automation is a plus.
• Strong written and verbal communication skills and the ability to work with multiple groups.
• Must be detail oriented with strong customer service skills.
• High level of PC skills with knowledge of MS Office Suite

Our total compensation package includes a comprehensive medical and dental insurance plan, 401K, employee stock purchase plan and 3 weeks of vacation.