Job Description

PEAK is looking for a Sr. Physical Design Engineer in ASIC/ SoC Place & Route with 5+ years of experience, APR, and actual hands-on work for San Jose, CA and Austin, TX locations. This is a direct/ full time role with a client of ours in the semiconductor industry.

YOU WILL BE RESPONSIBLE AND BE ABLE TO PERFORM THE FOLLOWING:

• Block level floorplan
• Clock tree synthesis
• Place & Route
• RC extraction
• STA
• Timing closure
• IR/EM analysis and fix
• DRC/LVS/ERC clean up
• Tape-out sign off
• Additional duties assigned by the supervisor

REQUIREMENTS:

• Education: Bachelor/Master’s degree in Electrical Engineering or Computer Science

• 2-20 years Netlist (or RTL)-GDS physical implementation experience

• In depth knowledge of major EDA tools/design flows

• Experience in block level implementation or chip integration and signoff

• Experience in Perl/TCL language programming

• Proven record in multi-million gate design production tape-out

• Proven ability to analyze issues, solve problems and bring closure

• Quality of execution and able to execute tasks assigned by the supervisor and customers and acquire the necessary skills to execute assignments

• Experience in any of the following is a plus:

• Low-power implementation methodology

• Advanced timing signoff methodology

• Able to independently complete Netlist-GDS P&R and signoff task

Company Description

www.peaktechnical.com