SAPEON: We make AI happen

It is an exciting time to join SAPEON. We aim to provide universal AI services to everyone by serving the vision of a happier, more enriched humanity.

SAPEON is a cutting-edge technology company specializing in developing AI-based semiconductor chips and systems. Our team of computer science, electrical engineering, and AI research experts is dedicated to pushing the boundaries of what is possible. We constantly look for new and innovative ways to develop and apply our technology to real-world problems.

Our flagship product is a series of AI-specific semiconductor chips designed to deliver unparalleled performance and efficiency in machine learning and deep learning applications. These chips are used in various industries, including security, media, manufacturing, mobility, automotive, and more.

At SAPEON, we are committed to creating a better future through the application of AI and related technologies. We invite you to join our journey to support humanity that is greener yet more capable than ever. We believe that our products and services can make a real impact wherever AI exists.

The Role

The NPU (Neural Processing Unit) Microarchitect will be responsible for RTL design and optimization for Power/Performance/Area (PPA) in Sapeon’s X series chips. The candidate will have proven industry experience writing RTL code for either NPUs (Machine Learning Accelerators), CPUs or GPUs. In this role, the candidate will work directly with the Architecture team to design and implement new NPU processors as well as improving on existing designs. The candidate should have a strong background in computer architecture and be able to work cross-functionally across teams that span across DV/AI applications/SW. It is expected that the designer will apply innovative approaches for implementing NPU processor blocks in a power and area-efficient manner. An ideal team member is courageous when it comes to trying new things, is adept at reasoning about systems performance, and is willing to iterate RTL for successively better implementation.

Responsibilities include

• Defining new microarchitecture and optimizing existing NPU building blocks through writing power and area efficient RTL. The overall goal is to improve performance/power/area metrics and provide flexibility for different neural networks
• Use innovative approaches to improve NPU microarchitecture and document these in Micro-Architectural Specs
• Assess feasibility of new and innovative ideas and refine them through successively better RTL implementations
• Write unit level, directed and transactional testbenches in the absence of dedicated DV engineers

Qualifications

• 5+ years of experience in hardware design at the RTL level on one of the following designs: NPU (ML accelerator), CPU or GPU.
• Experience in writing PPA (power/performance/area) optimized RTL code in Verilog/SystemVerilog, preferably in an industrial, revenue generating product
• Scripting skills in Python/PERL or another scripting language to improve productivity
• Desire to contribute to writing interfaces for other silicon development such as intra-die interconnect, inter-die interconnect, DVFS controllers and caches

Preferred qualifications

• Experience with writing testbenches in SystemVerilog
• Experience in NPU, GPU, and micro-processor development; especially many-core and multi-chip systems
• Experience with ML networks and ML frameworks (Tensorflow, PyTorch, TVM, and so on)
• Exposure to CUDA/OpenCL or some other parallel programming language
• Familiar with neural network compiler development and/or operating systems

Benefits

• Competitive compensation + equity grant
• Medical/Dental/Vision/Life Insurance with no premium deduction
• Retirement plan with company matching
• PTO and paid holidays