Job Description

• Needs to be familiar with all aspects of ASIC integration including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration
• Familiar with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions
• Familiar with physical assembly flows and physical verification flow for both block level and chip level
• Experience with large SoC designs (>30M gates) with frequencies in excess of 1.5GHz utilizing state of the art deep sub 12nm/7nm technologies and/or below process

Qualifications

• Familiar with foundry related issues.
• Good experience with Calibre physical verification and tapeout procedures
• Good understanding of Synthesis, SDC, Timing requirements
• Good handle of Perl/TCL
• Nice to have FCR experience
• Nice to have  experience and have good understanding of Synopsys library/database management
• BSEE with 12+ years of hands-on experience

Additional Information All your information will be kept confidential according to EEO guidelines.

While the COVID-19 vaccination is highly encouraged for the health and safety of our team members, it is not a requirement to demonstrate proof of vaccination at this time. As this is a fluid situation, we will continue to monitor legal developments in this space and update our guidance accordingly. All team members are expected to comply with applicable local, state, and federal law.