Job Description

ASIC DESIGN ENGINEER III - COMPUTER HARDWARE INDUSTRY Location: Irvine, CA Pay Rate: $78.57/hr Start Date: ASAP 6 Month Contract Role (Potential for Extension or Conversion) Job Category: Engineering

Our client is seeking an "ASIC Design Engineer III" for driving Clock Domain Crossing (CDC) closure across for next generation enterprise SSD SOC controller. The candidate should possess a deep understanding of the entire ASIC design process from architecture thru timing closure with extensive experience in asynchronous design and clock domain crossing.

Duties:

• Work with relevant team member to set up a robust CDC flow and policy
• Drive the design team to adherence of the established CDC policies with a goal of having zero waivers
• Review and audit designers' modules and CDC reports
• Provide expert input in identifying the areas of concerns and how to resolve them
• Track and report progress to the SoC lead and management
• Drive to a design with zero CDC waivers thru design correction or CDC constraint application
• Establish process to review and verify that any constraints are valid and the design is correct with no ambiguity

Education & Experience:

• Previous technical leadership experience
• Proven ability to troubleshoot and analyze complex problems
• Ability to multi-task and meet deadlines
• Should be a fast learner and a good team player
• Comfortable working in a global multi-site ASIC team for enterprise SSD controller development.
• Able to work independently, plan tasks/sub-tasks and report progress on weekly basis.
• Prior knowledge of scripting languages like Perl, Python or Tcl is a plus.

Please submit your resume in Word or PDF version to be considered.

Company Description

The TPS Group, www.tpsmithgroup.com, is a Certified Woman and Disabled Owned Diverse recruiting and staffing firm that is a trusted recruiting partner to top companies.