Velodyne Lidar is an industry leader building smart lidar solutions for autonomy and driver assistance. Headquartered in San Jose, CA, Velodyne is known worldwide for its portfolio of breakthrough lidar sensor technologies. Our lidar technology has revolutionized perception and autonomy for automotive, new mobility, mapping, robotics, and security applications.Velodyne Lidar is looking for an Intern to work on digital design ASICs for lidar signal processing. In this role, you will work improving design flows and system integration flows. You should have hands-on experience with scripting using perl/python with understanding of digital design flows. You will be collaborating with other disciplines of analog ASIC design, FPGA, and system integration engineers.Job ResponsibilitiesWork with the SOC design team for RTL design and integration.Work with logic design engineers to fully automate the CSV to system Verilog register generation.Write scripts to cross check the quality of SOC integration at various integration steps.Perform digital design work across all aspects of the design flow from RTL to GDS.Job RequirementsFamiliar with system Verilog and interface coding style.Hands-on experience with Perl scripting.Experience with ASIC design and SOC flowsExperience with Cadence’s xcelium/incisive simulation tools and able to use simvision for waveform viewing.Preferred Education and Experience RequirementsBSEE, MSEE or PhD of relevant experience in Digital ASIC design and integrationExperience with digital design processes is a plus.Velodyne is an equal opportunity employer and does not discriminate on the basis of race, color, religion, sex, national origin, gender identity, sexual orientation, veteran status, disability, age or other legally protected status.Note to all recruitment agencies: Velodyne Lidar does not accept agency resumes. Please do not forward resumes to our career page or any Velodyne employees. Velodyne is not responsible for any fees related to any unsolicited resumes.