Job Description

DESIGN VERIFICATION ENGINEER

Design Verification engineers with hands-on experience in multiple projects with development of System Verilog/UVM based verification environments from scratch.

REQUIRED:

• Bachelors or Masters in Electrical or Computer Science

• 3-5 years of relevant verification experience in UVM

• Ability to adapt to a start-up fast paced dynamic environment

• Hands on experience with development of System Verilog/UVM based verification environments from scratch.

• Experience with coverage driven verification methodologies using UVM.

• Experience with creating/executing test plans, coverage plans leading to successful tapeout.

• Good understanding of Processor architecture, Pipelines, Caches.

• Experience working on microprocessors, GPUs or other complex architectures. CPU experience is preferred buy not firm requirement.

• Ability to write assertions, cover properties, cover points.

PREFERRED:

• Knowledge of standard protocols like PCIe and DDR4/5 is a plus.
• CPU verification experience is highly desired.

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Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Visit https://www.yoh.com/applicants-with-disabilities to contact us if you are an individual with a disability and require accommodation in the application process.

Company Description

Investment Management Company