Avery Huang

Master's

Computer Science

Moore Threads Tech

C GPU Architect Architecture Memory Subsystem

- Simulated function and performance of GPU TLB, MMU, and cache bus interface in modern C++ within the full-chip - 10000 lines of code - Implemented a CUDA C++ framework to dissect micro-architecture of Nvidia GPUs. Analyzed cache latency, bandwidth, and Network-on-Chip utilization through benchmarking kernels - Purposed a configurable hash function for MMU cache bank interleaving, and a unified reversible hash function across - Designed double end-to-end bandwidth feature on arch to support 2x speedup of MMA operation on texture memory - Performed performance validation and analysis. Developed CUDA and OpenCL kernels exposing multiple address access