Benjamin Zhang

Bachelor's

Computer Engineering

VDHL, VIVADO, FPGA

- Https://git.io/JTow1 - Created an HLSM in VHDL for controlling a register file along with a test bench to verify its functionality using behavioral simulation - Developed a datapath and a controller to allow the user to load, view, and perform arithmetic operations on the contents of the register file - Constrained the inputs to buttons and switches using an FPGA board to analyze and prototype the system