Sai Chetana Kunapareddy

Master's

Electrical Engineering

PDK

- Fall 2023 - Designed a 2-bit adder, starting with Verilog code development and functional verification. The design underwent synthesis using Design Compiler - RTL to GDSII of Graph Convolutional Network (GCN) Design for Node Classification (7nm PDK - Engineered RTL for a GCN module tailored for 6-node classification, aligning with detailed design specifications and flow diagrams. Utilized - Synopsys Design Compiler for synthesis and Cadence Innovus for Place & Route, culminating in GDSII file generation. Conducted post-layout STA with PrimeTime, achieving desired timing closure, and verified functionality with ModelSim against golden standards post-RTL, synthesis, and APR - Executed physical verification using Calibre, clearing all DRC violations and ensuring LVS correctness, maintaining operational latency below 100ns through effective dynamic power reduction strategies - OTHER WORK EXPERIENCE